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温晓青教授学术报告信息
     日期:09-18
报告题目:From Low-Power Testing to Power-Safe Testing
报告时间: 2014年09月23日(周二)上午9:30-11:00
报告地点: 斛兵楼学术报告厅
报告人:   温晓青教授(日本九州工业大学)
报告内容简介:
     Advances in hardware/software-based power management have significantly driven down functional power dissipation of VLSI circuits; however, they have also widened the gap between functional and test power, resulting in excessive-test-power-induced yield loss. Although numerous power-aware test techniques have been proposed in the past decade for reducing test power, testing for power management circuitry, and streamlining power management in the complete design-and-test flow, many of them still suffer from such severe problems as unguaranteed test power safety, inflated test data, increased test time, nonnegligible area overhead, compromised test quality, and degraded performance. These problems make it necessary to take power-aware testing to the next stage, in which the focus should evolve from indiscriminate test power reduction to guaranteed test power safety. This talk will describe typical test-power-safe solutions for at-speed scan testing and scan-based logic BIST, followed by an introduction of important future research topics in the field of power-safe testing.
报告人简介:
     Xiaoqing Wen received a Bachelor degree from Tsinghua University, China, in 1986, a Master degree from Hiroshima University, Japan, in 1990, and a Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was also a Visiting Researcher at University of Wisconsin - Madison, USA, from October 1995 to March 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its Chief Technology Officer until 2003. In 2004 he joined Kyushu Institute of Technology, Japan, where he is currently a Professor and Director of Dependable Integrated Systems Research Center. His research interests include VLSI testing, diagnosis, and testable designs. He has co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability, and Power-Aware Testing and Test Strategies for Low Power Devices. He holds 38 U.S. Patents and 14 Japan Patents on VLSI testing. He received IEICE-ISS Best Paper Award in 2008. He is a fellow of IEEE and a trustee of REAJ. More information can be found at http://aries3a.cse.kyutech.ac.jp/~wen/.
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